A semiconductor chip consists of an array of devices whose contacts are interconnected by patterns of metal wiring. In very large scale integration (VLSI) chips, these metal patterns are multilayered and are separated by layers of an insulating material, characterized by a dielectric constant. Interlevel contacts between metal wiring layers are made by through-holes or vias, which are etched through the layers of the insulating material. Typical integrated circuit chip designs utilize one or more wiring levels. Insulating or dielectric materials are employed between the wires in each level (intralevel dielectric) and between the wiring levels (interlevel dielectric).
In VLSI chips, the insulating material is typically silicon dioxide with a dielectric constant epsilon of about 3.9 to about 4.1. As the speed requirements of the chip are increased, the RC value of the circuits must be reduced such as by reducing the circuit capacitance. The quest for higher density or integration on chips results in shrinking dimensions which tends to increase the circuit capacitance. Thus there is a need in the future for a dielectric material or structure with a reduced effective epsilon. Dielectric materials or structures with lower dielectric values are being investigated as replacements for the silicon dioxide insulator. However, some materials with significantly lower dielectric constants are thermally unstable at temperatures required to process or manufacture the VLSI chips.
In U.S. Pat. No. 4,169,000 which issued on Sept. 25, 1979 to J. Riseman and assigned to the assignee herein, an air-isolated integrated circuit structure with a planar wirable surface is described. Cavities were etched into the substrate and a silicon dioxide layer was formed over the substrate and cavities. Next, a silicon dioxide layer supported by another substrate is abutted and fused to the original silicon dioxide layer enclosing the air cavities. The supporting substrate over the fused silicon dioxide layer is removed leaving a planar dielectric surface.
In U.S. Pat. No. 5,461,003 which issued on Oct. 24, 1995 to R. H. Havemann et al., a method for forming air gaps between metal leads of a semiconductor device is described. A disposable solid layer is formed between metal leads. A porous dielectric layer is then formed over the disposable solid layer and the metal leads. The disposable solid layer is then removed through the porous dielectric layer to form air gaps between the metal leads beneath the porous dielectric layer.
A structure and method for making multilevel air bridge wiring is described in a publication by J. E. Cronin et al. IBM TDB 32/8A 88 (January 1990). An earlier publication published anonymously, IBM TDB 31/4 266 (September 1988) described a partially-supported bridge structure.